//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module LINF_OVSAMPLE(
   input                LINF_RESET,

   input                RFCLK_CLOCK311_0,
   input                RFCLK_CLOCK311_45,
   input                RFCLK_CLOCK311_90,
   input                RFCLK_CLOCK311_135,
   input                RFCLK_CLOCK155,

   input                AFE_RXD,

   output[15:0]         OVSMP_OUT_DATA
     ) ;


wire[7:0]              LINE_OVS_RX_DATA;
reg                    DS00 ,DS01 ,DS02 ,DS03 ,DS04 ,DS05 ,DS06 ,DS07;
reg                    DS10 ,DS11 ,DS12 ,DS13;
reg                    DS14N,DS15N,DS16N,DS17N;
reg                    DS20 ,DS21 ,DS22 ,DS23 ,DS24 ,DS25 ,DS26 ,DS27;
wire[7:0]              DS_DATA ;

reg                    DWEX_CNT2;
reg[7:0]               DWEX_WORD_0, DWEX_WORD_1;
reg[15:0]              DWEX_DATA_311;
reg[15:0]              DWEX_DATA_155;

// reg[7:0]               LIN_OVS_KEEPER;

// lcell     input_ds0 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[0]));
// lcell     input_ds1 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[1]));
// lcell     input_ds2 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[2]));
// lcell     input_ds3 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[3]));
// lcell     input_ds4 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[4]));
// lcell     input_ds5 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[5]));
// lcell     input_ds6 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[6]));
// lcell     input_ds7 (.in(AFE_RXD), .out(LINE_OVS_RX_DATA[7]));


// always @( posedge RFCLK_CLOCK155 ) begin
//   LIN_OVS_KEEPER                  <= LINE_OVS_RX_DATA;
//end
//  assign OVSMP_KEEPER   = LIN_OVS_KEEPER;




always @( posedge RFCLK_CLOCK311_0 )  begin
      DS00                        <= AFE_RXD;
end
always @( posedge RFCLK_CLOCK311_45 )  begin
      DS01                        <= AFE_RXD;
end
always @( posedge RFCLK_CLOCK311_90 )  begin
      DS02                        <= AFE_RXD;
end
always @( posedge RFCLK_CLOCK311_135 )  begin
      DS03                         <= AFE_RXD;
end
always @( negedge RFCLK_CLOCK311_0 )  begin
      DS04                         <= AFE_RXD;
end
always @( negedge RFCLK_CLOCK311_45 )  begin
      DS05                         <= AFE_RXD;
end
always @( negedge RFCLK_CLOCK311_90 )  begin
      DS06                         <= AFE_RXD;
end
always @( negedge RFCLK_CLOCK311_135 )  begin
      DS07                         <= AFE_RXD;
end

always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 ) begin
        DS10                       <=1'b0;
        DS11                       <=1'b0;
        DS12                       <=1'b0;
        DS13                       <=1'b0;
   end
   else begin
        DS10                       <=DS00 ;
        DS11                       <=DS01 ;
        DS12                       <=DS02 ;
        DS13                       <=DS03 ;
   end
end
always @( negedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 ) begin
        DS14N                      <=1'b0 ;
        DS15N                      <=1'b0 ;
        DS16N                      <=1'b0 ;
        DS17N                      <=1'b0 ;
   end
   else begin
        DS14N                      <=DS04 ;
        DS15N                      <=DS05 ;
        DS16N                      <=DS06 ;
        DS17N                      <=DS07 ;
   end
end

always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 ) begin
        DS20                       <= 1'b0;
        DS21                       <= 1'b0;
        DS22                       <= 1'b0;
        DS23                       <= 1'b0;
        DS24                       <= 1'b0;
        DS25                       <= 1'b0;
        DS26                       <= 1'b0;
        DS27                       <= 1'b0;
   end
   else begin
        DS20                       <= DS10 ;
        DS21                       <= DS11 ;
        DS22                       <= DS12 ;
        DS23                       <= DS13 ;
        DS24                       <= DS14N;
        DS25                       <= DS15N;
        DS26                       <= DS16N;
        DS27                       <= DS17N;
   end
end



assign  DS_DATA[7:0] ={DS20 ,DS21 ,DS22 ,DS23 ,DS24 ,DS25 ,DS26 ,DS27} ;

always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 )
        DWEX_CNT2                              <=1'b0;
   else
        DWEX_CNT2                              <=DWEX_CNT2 +1'b1;
end

always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 )
      DWEX_WORD_0[7:0]                         <= 8'd0;
   else if ( DWEX_CNT2==1'b0 )
      DWEX_WORD_0[7:0]                         <= DS_DATA[7:0];
end
always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 )
      DWEX_WORD_1[7:0]                         <= 8'd0;
   else if ( DWEX_CNT2==1'b1 )
      DWEX_WORD_1[7:0]                         <= DS_DATA[7:0];
end

always @( posedge RFCLK_CLOCK311_0 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 )
      DWEX_DATA_311[15:0]                      <=16'd0;
   else if ( DWEX_CNT2==1'b0 )
      DWEX_DATA_311[15:0]                      <={DWEX_WORD_0[7:0], DWEX_WORD_1[7:0]};
end

always @( posedge RFCLK_CLOCK155 or posedge LINF_RESET)  begin
   if ( LINF_RESET==1'b1 )
      DWEX_DATA_155[15:0]                      <=16'd0;
   else
      DWEX_DATA_155[15:0]                      <=DWEX_DATA_311[15:0];
end

  assign OVSMP_OUT_DATA[15:0]    = DWEX_DATA_155[15:0];


endmodule
